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| NTD4910N Power MOSFET Features 30 V, 37 A, Single N-Channel, DPAK/IPAK * * * * Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb-Free Devices V(BR)DSS 30 V http://onsemi.com RDS(on) MAX 9.0 mW @ 10 V 13 mW @ 4.5 V D ID MAX 37 A Applications * CPU Power Delivery * DC-DC Converters MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (RqJA) (Note 1) Power Dissipation (RqJA) (Note 1) Continuous Drain Current (RqJA) (Note 2) Power Dissipation (RqJA) (Note 2) Continuous Drain Current (RqJC) (Note 1) Power Dissipation (RqJC) (Note 1) Pulsed Drain Current tp=10ms Current Limited by Package TA = 25C TA = 100C TA = 25C TA = 25C Steady State TA = 100C TA = 25C TC = 25C TC = 100C TC = 25C TA = 25C TA = 25C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 30 "20 11.2 7.9 2.6 8.2 5.8 1.37 37 26 27.3 152 60 -55 to 175 23 7.0 25.3 W A A C A V/ns mJ W A W A Unit V V A G S 4 4 12 N-Channel 4 3 1 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 CASE 369AD CASE 369D IPAK IPAK (Straight Lead) (Straight Lead DPAK) 23 1 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain YWW 49 10NG 4 Drain YWW 49 10NG 4 Drain Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, VDD = 50 V, VGS = 10 V, L = 0.1 mH, IL(pk) = 22.5 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s) TL 260 C 2 1 23 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4910N G = Year = Work Week = Device Code = Pb-Free Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. (c) Semiconductor Components Industries, LLC, 2009 June, 2009 - Rev. 0 1 Publication Order Number: NTD4910N/D YWW 49 10NG NTD4910N THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction-to-Case (Drain) Junction-to-Tab (Drain) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State (Note 4) 3. Surface-mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 4. Surface-mounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJC-TAB RqJA RqJA Value 5.5 4.3 58.5 109.7 Unit C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = 10 V VGS = 4.5 V Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(on) tr td(off) tf td(on) tr td(off) tf VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 11.6 21.8 16.5 4.2 7.3 19.5 20.2 2.0 ns ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A 1203 VGS = 0 V, f = 1.0 MHz, VDS = 15 V 460 12.5 6.8 1.95 3.9 1.1 15.4 nC nC pF gFS ID = 30 A ID = 15 A ID = 30 A ID = 15 A VDS = 1.5 V, ID = 30 A VGS = VDS, ID = 250 mA 1.0 1.6 4.0 7.5 7.5 10.6 10.6 40 S 13 9.0 2.2 V mV/C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 24 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 30 15 1.0 10 "100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = "20 V 5. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD4910N ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD tRR ta tb QRR LS LD LD LG RG TA = 25C VGS = 0 V, dIs/dt= 100 A/ms, IS = 30 A VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.91 0.82 27 14 13 17 nC ns 1.1 V Symbol Test Condition Min Typ Max Unit Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance (Note 7) Drain Inductance, DPAK Drain Inductance, IPAK (Note 7) Gate Inductance (Note 7) Gate Resistance 7. Assume terminal length of 110 mils. 2.99 0.0164 1.88 4.9 1.0 2.0 nH W ORDERING INFORMATION Order Number NTD4910NT4G NTD4910N-1G NTD4910N-35G Package DPAK (Pb-Free) IPAK (Pb-Free) IPAK Trimmed Lead (Pb-Free) Shipping 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NTD4910N TYPICAL CHARACTERISTICS 60 10 V 7V 4.5 50 4.2 4.0 40 30 20 10 0 3.8 V VGS = 3.6 V TJ = 25C ID, DRAIN CURRENT (A) 3.4 V 3.2 V 3.0 V 2.8 V 2.6 V 2.4 V 0 1 2 3 4 0 2.0 2.5 60 50 40 30 TJ = 25C 20 TJ = 125C 10 TJ = -55C 3.0 3.5 4.0 VDS = 10 V ID, DRAIN CURRENT (A) VDS, DRAIN-TO-SOURCE VOLTAGE (V) VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 ID = 30 A TJ = 25C RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0.005 0.004 Figure 2. Transfer Characteristics TJ = 25C VGS = 4.5 V VGS = 10 V 15 25 35 45 55 VGS (V) ID, DRAIN CURRENT (A) Figure 3. On-Resistance vs. VGS 10,000 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 Figure 4. On-Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150C 2.0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 TJ = 125C 100 TJ = 85C 0.6 -50 -25 0 25 50 75 100 125 150 175 10 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 4 NTD4910N TYPICAL CHARACTERISTICS VGS = 0 V TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (V) 1600 Ciss 15.0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 Qgd Qgs VDD = 15 V VGS = 10 V ID = 30 A 0 2 4 6 8 10 12 14 16 18 20 TJ = 25C QT C, CAPACITANCE (pF) 1200 800 Coss 400 Crss 0 5 10 15 20 25 30 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 0 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1000 IS, SOURCE CURRENT (A) VDD = 15 V ID = 15 A VGS = 10 V t, TIME (ns) 100 30 25 20 15 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge VGS = 0 V td(off) tf tr TJ = 125C 10 5 0 TJ = 25C 0 0.2 0.4 0.6 0.8 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (V) 10 td(on) 1 1 10 RG, GATE RESISTANCE (W) 100 Figure 9. Resistive Switching Time Variation vs. Gate Resistance EAS, SINGLE PULSE DRAIN-TO- SOURCE AVALANCHE ENERGY (mJ) 1000 30 Figure 10. Diode Forward Voltage vs. Current ID = 24 A 25 20 15 10 5 0 ID, DRAIN CURRENT (A) 100 10 ms 10 VGS = 10 V Single Pulse TC = 25C RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 100 ms 1 ms 10 ms dc 1 0.1 100 25 50 75 100 125 150 175 VDS, DRAIN-TO-SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTD4910N TYPICAL CHARACTERISTICS 100 10 R(t) (C/W) 1 0.1 0.01 0.001 Psi Tab-A 0.000001 0.00001 0.0001 0.001 0.01 PULSE TIME (sec) 0.1 1 10 100 1000 Duty Cycle = 50% 20% 10% 5% 2% 1% Single Pulse Figure 13. FET Thermal Response 70 60 50 GFS (S) 40 30 20 10 0 0 10 20 30 ID (A) 40 50 60 VDS = 1.5 V Figure 14. GFS vs. ID http://onsemi.com 6 NTD4910N PACKAGE DIMENSIONS DPAK CASE 369AA-01 ISSUE A -T- B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 --- 0.89 1.27 3.93 --- C E S A 1 2 3 Z H U F L D 2 PL J DIM A B C D E F H J L R S U V Z 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTD4910N PACKAGE DIMENSIONS IPAK (STRAIGHT LEAD DPAK) CASE 369D-01 ISSUE B E Z DIM A B C D E F G H J K R S V Z B V R 4 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- S -T- SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN E L2 E3 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD-01 ISSUE O A A1 E2 L1 D L b1 2X D2 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 --- 6.35 6.73 4.70 --- 4.45 5.46 2.28 BSC 3.40 3.60 --- 2.10 0.89 1.27 T SEATING PLANE A1 A2 3X e b 0.13 M E2 D2 T OPTIONAL CONSTRUCTION ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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